1. Field of the Invention
This invention relates to a programmable IC card having a semiconductor memory, i.e., a PROM (programmable read only memory) card, in which data can be stored after the card has been assembled, and, more particularly, to the internal circuitry of the PROM card.
2. Description of Related Art
Generally, there are two types of IC memory cards: ROM cards and RAM cards, as described in "IC MEMORY CARD GUIDELINE" (issued September 1986) by the Personal Computer Business Committee of Japan Electrical Industry Development Association. ROM cards are separated into two groups: mask ROM cards in which data cannot be written after the card has been assembled; and OTP (one time programmable) memory cards or EPROM (electrically programmable read only memory) memory cards in which data can be written by using a writing device on the market called a PROM (programmable read only memory) writer after the card has been assembled. The difference between an OTP card and an EPROM card resides in whether or not rewriting is possible. OTP cards can only be programmed one time. The present invention will be described hereinafter with respect to OTP cards.
FIG. 1 shows a fundamental construction of an internal circuit of a conventional OTP card. The OTP card has an OTP memory 1 into which data can be written. To this memory are connected a power supply line [Vcc] 2 through which the memory 1 is supplied with power, a ground line [GND] 3, a write power supply line [Vpp] 4 for supplying power at the time of writing, an address bus [ADD] 5, a data bus [DATA] 6, a card enable control line or chip enable control line [CE] 7 for controlling the operation of the memory 1, and an output enable control line [OE] 8. These signal lines are combined at an input/output connector 9 and may be connected to, e.g., a terminal unit. The OTP card illustrated in FIG. 1 incorporates only one OTP memory and has a simple construction. However, the construction of a different OTP card incorporating a plurality of OTP memories is basically the same as the illustrated example. OTP memories having of 256 kilo-bit or 32 memory capacities, e.g., "M5L27C256" and M5L27C32" are most popularly used. The states of the input control signal lines at the time of reading and writing are as shown in Table 1:
TABLE 1 ______________________________________ (volt) Operation ##STR1## ##STR2## Vpp 4 Vcc 2 ______________________________________ Read VIL VIL 5 V 5 V Write VIL VIH 12.5 V 6 V ______________________________________ VIL = 0 to 0.8 V VIH = 2 to approximately Vcc V
That is, at the time of reading, the voltages of the card enable control line [CE] 7 and the output enable control line [OE] 8 are set to VIL (low level). In this state, an address is input through the address bus 5, and data read out then appears on the data bus 6. At the time of writing, the voltage of the output enable control line [OE] 8 is set to VIH (high level), and the voltage of the write power supply line 4 is set to 12.5 V. In this state, an address is input through the address bus 5, data to be written is set on the data bus 6, and the level of the card enable control line [CE] 7 is maintained at VIL for a certain period of time, thereby writing the data.
FIG. 2 is a flow chart of a process of writing in or reading from this OTP memory. In step S1 of FIG. 2, an address signal is set to the initial 0 address. In step S2, various control signals for data writing are prepared in accordance with Table 1. In step S3, data to be written is prepared and written. In step S4, whether or not the address is the final one is determined. If it is not the final address, the address is incremented by one in step S5, and the process returns to step S3. In step S6, the various control signals are prepared in accordance with Table 1 to read out data written in the OTP memory. In step S7, data corresponding to input addresses are read out in a random manner. In this flow chart, the steps S1 to S5 correspond to writing and the steps S6 and S7 correspond to reading. Thus, writing in and reading from the OTP memory are performed. It is of course possible to operate an IC memory card incorporating the OTP memory in the same manner.
The conventional ROM card in which data can be written is thus constructed, and the anti-electrostatic performance of the card, i.e., ESD (electrostatic discharge) resistance, is limited to that of the OTP memory. If a plurality of OTP memories are incorporated in an IC memory card, the OTP memories are connected to the data bus 6 in parallel with each other, and the fan-in/fan-out conditions are changed depending upon the number of OTP memories, i.e., the total memory capacity of the OTP memory card. As a result, the interface circuit becomes complicated.